Integrated circuit devices, such as high speed semiconductor memory devices, typically input and output data in-synch with an externally applied clock signal. For example, in a high speed semiconductor memory device, data input and output operations may utilize an internal clock signal synchronized with the phase of the external clock signal. The internal clock signal is typically generated by an internal clock signal generating circuit using a delay locked loop (DLL) circuit.
The internal clock signal is transmitted to various internal circuits using a clock signal to control their operation, such as input and output circuits placed near input and output pads, via a clock line. The transmitted clock signals, referred to as a local clock signals in the vicinity of the internal circuits, drive an associated input and output circuit.
However, in a conventional high speed semiconductor memory device, clock lines typically take the form of a clock net which has a clock tree structure. The tree structure transmits the internal clock signal from an output port of the internal clock signal generating circuit to a plurality of internal circuits such as input/output circuits. A clock tree typically has different loads, i.e., different parasitic resistances and parasitic capacitances depending on its length. Therefore, the delay time generally varies according to the length of the clock tree. Accordingly, a phase difference may be generated between the transmitted local clock signals in the vicinity of the input/output circuits. The data input/output performance of integrated circuit devices, such as a high speed semiconductor memory devices, may be degraded as a result of the phase difference.
In another aspect of internal clock generation, a conventional internal clock signal generating circuit used in devices, such as high speed semiconductor memory devices, typically includes a conventional Delay Lock Loop ("DLL") circuit. The DLL circuit generally includes a delay monitoring circuit which generates a delay time intended to be the same as a delay time produced by the internal circuits carrying the internal clock signal including, for example, a clock signal buffer, a clock signal line, and an input/output circuit. Such a conventional DLL circuit typically generates an internal clock signal using the phase difference between a feedback clock signal output by the delay monitoring circuit and an external clock signal. However, the delay monitoring circuit in such a conventional DLL circuit typically has a complicated design, has a large layout area, and consumes a large amount of power. Also, when temperature, supplied voltage, noise, and/or the manufacturing process are changed, the delay time generated by the delay monitoring circuit may become widely different from the delay time generated by the clock net and the input/output circuits. Therefore, the performance of the high speed semiconductor memory device can be degraded.